Ultra-fast detector for wide range spectral measurements

KALYPSO is a novel detector operating at line rates above 10 Mfps. The detector board holds a silicon or InGaAs linear array sensor with spectral sensitivity ranging from 400 nm to 2600 nm. The sensor is connected to a cutting-edge, custom designed, ASIC readout chip which is responsible for the remarkable frame rate. The FPGA readout architecture enables continuous data acquisition and processing in real time. This detector is currently employed in many synchrotron facilities for beam diagnostics and for the characterization of self-built Ytterbium-doped fiber laser emitting around 1050 nm with a bandwidth of 40 nm

EXAMPLES OF MEDICAL SOFTWARE AND HARDWARE EXPERT SYSTEMS FOR DYSFUNCTION ANALYSIS AND TREATMENT

Paper present the recent research in DMCS. The medical and biometric research projects are presented. One of the key element is an image acquisition and processing. The paper presents research of diagnostic application of voice analysis for stroke patients with speech dysfunction, as well as the method for diagnosing and monitoring the effectiveness of medical rehabilitation of patients with dysfunction of the cervical spine. Then the method for sudden cardiac death risk stratification is elaborated

RECENT RESEARCH IN VLSI, MEMS AND POWER DEVICES WITH PRACTICAL APPLICATION TO THE ITER AND DREAM PROJECTS

Several MEMS (Micro Electro-Mechanical Systems) devices have been analysed and simulated. The new proposed model of SiC MPS (Merged PIN-Schottky) diodes is in full agreement with the real MPS devices. The real size DLL (Dynamic Lattice Liquid) simulator as well as the research on modelling and simulation of modern VLSI devices with practical applications have been presented. In the basis of experience in the field of ATCA (Advanced Telecommunications Computing Architecture) based systems a proof-of-concept DAQ (data acquisition) system for ITER (International Thermonuclear Experimental Reactor) have been proposed

High-Performance Image Acquisition and Processing for Stereoscopic Diagnostic Systems with the Application of Graphical Processing Units

In recent years, cinematography and other digital content creators have been eagerly turning to Three-Dimensional (3D) imaging technology. The creators of movies, games, and augmented reality applications are aware of this technology’s advantages, possibilities, and new means of expression. The development of electronic and IT technologies enables the achievement of a better and better quality of the recorded 3D image and many possibilities for its correction and modification in post-production. However, preparing a correct 3D image that does not cause perception problems for the viewer is still a complex and demanding task. Therefore, planning and then ensuring the correct parameters and quality of the recorded 3D video is essential. Despite better post-production techniques, fixing errors in a captured image can be difficult, time consuming, and sometimes impossible. The detection of errors typical for stereo vision related to the depth of the image (e.g., depth budget violation, stereoscopic window violation) during the recording allows for their correction already on the film set, e.g., by different scene layouts and/or different camera configurations. The paper presents a prototype of an independent, non-invasive diagnostic system that supports the film crew in the process of calibrating stereoscopic cameras, as well as analysing the 3D depth while working on a film set. The system acquires full HD video streams from professional cameras using Serial Digital Interface (SDI), synchronises them, and estimates and analyses the disparity map. Objective depth analysis using computer tools while recording scenes allows stereographers to immediately spot errors in the 3D image, primarily related to the violation of the viewing comfort zone. The paper also describes an efficient method of analysing a 3D video using Graphics Processing Unit (GPU). The main steps of the proposed solution are uncalibrated rectification and disparity map estimation. The algorithms selected and implemented for the needs of this system do not require knowledge of intrinsic and extrinsic camera parameters. Thus, they can be used in non-cooperative environments, such as a film set, where the camera configuration often changes. Both of them are implemented with the use of a GPU to improve the data processing efficiency. The paper presents the evaluation results of the algorithms’ accuracy, as well as the comparison of the performance of two implementations—with and without the GPU acceleration. The application of the described GPU-based method makes the system efficient and easy to use. The system can process a video stream with full HD resolution at a speed of several frames per second

KALYPSO: Linear Array Detector with Continuous Read-Out at MHz Frame Rates

he novel linear array detector KALYPSO has been developed for beam diagnostics based on 1-dimensional profile measurements at high-repetition rate free-electron lasers (FEL) and synchrotron radiation facilities. The current version of KALYPSO has 256 pixels with a maximum frame rate of 2.7~MHz. The detector board, which comprises the radiation sensor, analog signal amplification, and analog-to-digital signal conversion, has been designed as a mezzanine card that can be plugged onto application-specific carrier boards for data pre-processing and transmission. Either a Si or InGaAs sensor can be mounted for the detection of visible or near infrared radiation. Results obtained in several beam diagnostics applications at the European XFEL and FLASH are presented to demonstrate the powerful capabilities of the KALYPSO detector

Automated Testing of MicroTCA.4 Modules

The Low Level Radio Frequency (LLRF) control system of the European X-Ray Free Electron Laser is designed using MicroTCA.4 standard. The real-time control system is composed of a few Advanced Mezzanine Cards (AMCs): timing, digitizer, digital controller and vector modulator modules. The DAMC-TCK7 digital controller module was developed as a high-performance low-latency data processing device. The DAMC-TCK7 card, based on Xilinx Kintex 7 FPGA device, provides all necessary resources required to implement the digital LLRF controller, i.e.: processing power, DRAM memory, flexible timing distribution and Rear Transition Module (RTM) controller. The module is equipped with various high-speed serial interfaces available on the AMC, Zone 3 connectors and front-panel that are capable of transferring data up to 12.5 Gbps each. More than 60 DAMC-TCK7 modules were fabricated for the XFEL accelerator. The manufactured modules should be carefully tested before they will be installed in the XFEL accelerator tunnel. A dedicated framework for automated testing of the DAMC-TCK7 modules was developed to simplify and accelerate the test procedure. This paper presents details of the automated test framework design and the results after tests of 60 DAMC-TCK7 modules. The framework is composed of a FPGA firmware, Linux driver and software that allows testing of all key components of the digital AMC module, like power supply, FPGA, memory, clock distribution, high-speed interfaces, IPMI controller and its sensors. The framework uses MMC (Module Management Controller) to verify the proper operation of power supply module, AMC and RTM management. The other modules are tested using the FPGA with dedicated firmware. As a result, a report in the PDF file format is generated

High-Speed Linear Camera for Electro-Optic Experiment

The poster presents an ultra-fast linear camera designed for use in high-energy physics experiments. The device will be presented in context of building the spectrometer for longitudinal beam charge profiling utilizing the electo-optic effect

The Clinical Utility of Systemic Immune-Inflammation Index Supporting Charlson Comorbidity Index and CAPRA-S Score in Determining Survival after Radical Prostatectomy—A Single Centre Study

The selection of candidates for the curative treatment of PCa requires a careful assessment of life expectancy. Recently, blood-count inflammatory markers have been introduced as prognosticators of oncological and non-oncological outcomes in different settings. This retrospective, monocentric study included 421 patients treated with radical prostatectomy (RP) for nonmetastatic PCa and aimed at determining the utility of a preoperative SII (neutrophil count × platelet count/lymphocyte count) in predicting survival after RP. Patients with high SIIs (≥900) presented significantly shorter survival (p = 0.02) and high SIIs constituted an independent predictor of overall survival [HR 2.54 (95%CI 1.24–5.21); p = 0.01] when adjusted for high (≥6) age-adjusted CCI (ACCI) [HR 2.75 (95%CI 1.27–5.95); p = 0.01] and high (≥6) CAPRA-S [HR 2.65 (95%CI 1.32–5.31); p = 0.006]. Patients with high scores (ACCI and/or CAPRA-S) and high SIIs were at the highest risk of death (p < 0.0001) with approximately a one-year survival loss during the first seven years after surgery. In subgroup of high CAPRA-S (≥6), patients with high ACCIs and high SIIs were at the highest risk of death (p <0.0001). Our study introduces the SII as a straightforward marker of mortality after RP that can be helpful in pre- and postoperative decision-making

Standardized Solution of Management Controller for MicroTCA.4

The Micro Telecommunications Computing Architecture (MTCA) standard is a modern platform, that is gaining popularity in the area of High Energy Physics (HEP) experiments. The standard provides extensive management, monitoring and diagnostics functionality. The hardware management is based on Intelligent Platform Management Interface (IPMI), that was initially developed for management and monitoring of complex computers operation. The original IPMI specification was extended and new functions required for MTCA hardware management, were added. The Module Management Controller (MMC) is required on each Advanced Mezzanine Card installed in MTCA chassis. The Rear Transition Modules (RTMs) require RMC management controller (Rear transition module Management Controller) that is specified in MTCA.4 extension specification. The commercially available implementations of MMC and RMC are expensive and do not provide the whole functionality that is required by specific HEP applications. Therefore, many research centers and commercial companies work on their own implementation of AMC or RTM controllers. The available implementations suffer because of lack of a standard and interoperability problems. The Authors developed a unified solution of management controller fully compliant to MTCA and MTCA.4 standards. The MMC v1.00 solution is dedicated for management of AMC and RTM modules. The MMC v1.00 is based on Atmel ATxmega MCU and can be fully customized by user or used as a drop-in-module without any modifications. The paper discusses the functionality of the MMC v1.00 solution. The implementation was verified with developed evaluation kits for AMC and RTM cards